The fabrication of a semiconductor device involves hundreds of steps, each of which must be executed as accurately as possible to achieve a high-yield, functioning device. The beginning steps of fabrication begin with an electrical schematic of the integrated circuit, which is converted to a design layout that is used to ultimately construct a lithographic mask. As device sizes have moved well into the submicron range and component density has significantly increased, the accuracy of the lithographic processes has diminished inasmuch as many of the feature sizes have become smaller than the wavelength that is used to expose the photoresist located on the silicon wafer. This, in turn, allows diffraction that can cause feature distortion. The critical dimension inaccuracies of these lithographic processes are addressed by adding dummy features in the mask configuration and through other simulation programs. However, while this often satisfactorily addresses critical dimension concerns, it fails to address device operational or electrical characteristics that vary from those predicted by the design layout modeling processes and that are influenced by spacing between multi-strip gate structures, both active and dummy structures.
One factor that affects the operational or electrical characteristics is attributable to the presence of shallow trench isolation structures adjacent to transistor gates. It is known that these shallow trench isolation structures cause a compressive stress effect in the silicon in which the MOSFET channel region is located. This phenomenon is known as shallow trench isolation stress effect or “STI” stress effect.
In the past, STI stress effect was less of an issue because of the large size of the gate oxide areas and general device size in that by the time the stress reached the middle of the channel, it had been substantially dissipated. However, as the size of these gate oxide areas has shrunk below the 0.25 micron range, the STI stress effect has grown in significance due to the relatively small device size. The reason for this is that when the edges of the STI come closer together, there is not enough distance between the edges for stress relief itself. The STI stress effect has been exacerbated by the even smaller devices found in present day submicron technologies. As a result, it affects the active channels of the MOSFETS. For example, STI stress effect has been found to cause drive current degradations in MOSFETS and has also been found to cause defect and device leakage.
Increased device density and decreased feature size have made sub-wavelength patterning routine in integrated circuit fabrication, and have required the development of the technique known as optical process, or proximity, correction (OPC). OPC is a process that is conducted to account for exposure variations that occur due to proximity effects during the lithographic process. OPC is basically a mask making process peculiar to each lithographic fabrication facility and varies from one lithographic fabrication facility to another. During the mask making process, the original images get printed onto masks differently based on each facility's mask formulation process. OPC may include changing the width of mask features, changing the spacing between these features, or adding geometry to features to result in on-substrate features which are closer to the design geometry.
As mentioned above, for very deep, sub-micron processes, it, is difficult to print onto silicon the exact desired device shape due to the exposure limitations inherent in the lithographic processes. Patterning is affected because features have become so small that the light photography does not replicate the features well, particularly at device sizes of 130 nm, 90 nm, 65 nm and below. For example, if a structure is initially designed to be a rectangle having sharp, 90 degree corners, there are some processes, based on the processing that is done at the lithographic fabrication laboratory, that results in rounded corners. These variations occur because the features have become so small that with optical processing, the wavelength is not small enough to print everything accurately due to reflections and diffractions from the mask. As a result, the desired image does not get printed accurately. To compensate for this, the targeted features on the mask are modified, using sophisticated software programs, such that they more accurately print the intended configuration. These modifications affect MOSFET performance in a non-trivial manner.
Accordingly, what is needed in the art is a method that compensates for the deficiencies presently found in current device fabrication processes, as discussed above.